1. Field of the Invention
The invention relates to a boundary scan circuit and to a testing method performed thereby, more particularly to a built-in self-testing method for an IEEE Std. 1149.1 boundary scan circuit and to an IEEE Std. 1149.1 boundary scan circuit with a built-in self-testing capability.
2. Description of the Related Art
Built-in self-test (BIST), which is defined as the testing of an integrated circuit through built-in hardware features, is a testing method which can overcome testing problems usually encountered when conducting tests for complex VLSI circuits. Chip level BIST architecture involves: a test pattern generator, such as a linear feedback shift register (LFSR), connected to input nodes of an application logic; an output response analyzer, such as a multiple input signature register (MISR), connected to output nodes of the application logic; and a test controller for controlling operation of the test pattern generator and the output response analyzer.
LFSRs are well studied and widely used in VLSI circuitry because they are simple and fairly regular in structure, which are important for VLSI implementation. They are also used extensively in design for testability (DFT) techniques because their shift property integrates easily with serial scan. Their good performance in pseudo-exhaustive and pseudo-random pattern generation, and their ability to compress the circuit output response also make them popular in BIST environments. FIGS. 1 and 2 respectively show the circuit designs of an LFSR and an MISR having the characteristic polynomial p(x)=1+c.sub.1 x+c.sub.2 x.sup.2 +. . . +c.sub.n x.sup.n.
Since BIST permits execution of the testing operation at the speed of the system clock, testing can be performed at a much shorter time than other known testing techniques. In addition, BIST does not require the use of an Automatic Test Equipment (ATE). However, the silicon area must be increased to accommodate the test pattern generator, the output response analyzer and the test controller. This results in a lower chip yield and in higher manufacturing costs.
Recent advancements in the field of electronics manufacturing, such as surface mount technology (SMT) and multi-chip module (MCM), have caused numerous testing problems at the board level. The IEEE has issued a boundary scan standard (IEEE Std. 1149.1) to help alleviate the problem of testing connections at this level.
IEEE Std. 1149.1 provides a framework for reducing the test costs at board level by reusing pre-existing test patterns to a component on a board regardless of how pins of the component are interconnected. FIG. 3 illustrates a boundary scannable board design. A boundary-scan cell is provided adjacent to each component pin so that signals at component boundaries can be controlled and observed to determine whether a short circuit or open circuit condition has occurred on the board, and to detect the presence of a fault in an integrated circuit on a circuit board. Also, in-circuit testing is achieved by mere use of a special instruction to shift the pre-existing test patterns to the chip boundary, thereby simplifying testing at the board level. Moreover, the input and output boundary-scan cells, which cooperate to form input and output boundary-scan registers, can facilitate design debugging and fault diagnosis since the boundary-scan registers can be used to sample data flowing through the component without interfering with normal operation of the latter.
Referring to FIG. 4, a conventional boundary-scan cell of an IEEE Std. 1149.1 boundary scan circuit is shown to comprise a two-channel first multiplexer 11, a D-type first flip-flop 12, a D-type second flip-flop 13, and a two-channel second multiplexer 14. The first multiplexer 11 has a first data input which serves as a signal input, a second data input which serves as a scan input, a channel select input which receives a first control signal ShiftDR, and an output. The first flip-flop 12 has a data input connected to the output of the first multiplexer 11, a clock input for receiving a first clock signal ClockDR, and an output which serves as a scan output. The second flip-flop 13 has a data input connected to the output of the first flip-flop 12, a clock input for receiving a second clock signal UpdateDR, and an output. The second multiplexer 14 has a first data input which serves as a signal input, a second data input which is connected to the output of the second flip-flop 13, a channel select input which receives a second control signal Mode, and an output which serves as a signal output.
Referring to FIG. 5, the boundary scan test circuitry includes a test access port (TAP) system. Testing is performed by shifting test instructions and test data into the boundary-scan component via the TAP system. The TAP system is a 16-state system and has several input ports and one output port. These ports include: Test Data In (TDI) which provides serial inputs for test instructions shifted into the instruction register and for data shifted through the boundary-scan register or other test data registers; Test Data Out (TDO) which is the serial output for test instructions and data from the test data registers; Test Clock (TCK) which provides the clock for the test logic and which is a dedicated input that allows the serial test data path to be used independent of component-specific system clocks and that permits shifting of test data concurrently with normal component operation; Test Mode Select (TMS) which cooperates with TCK to cause operation of the TAP system from one state to another; and Test Reset (TRST*) which is an active-low input signal that provides asynchronous initialization of the TAP system.
Boundary scan test functions are accomplished via various test instructions which are defined by IEEE Std. 1149.1. Three of these test instructions, EXTEST, SAMPLE/PRELOAD and BYPASS, are mandatory for every boundary-scan device.
The EXTEST instruction is concerned primarily with testing of circuitry external to the device using the boundary-scan register of the device. A test vector is pre-loaded into the boundary-scan register, and the EXTEST instruction is used to drive the test vector to the external circuitry. When the EXTEST instruction is used to test the interconnection line, a test pattern is pre-loaded into the output boundary-scan register of one device and is then propagated to the next device. The response is latched on the input cells and is shifted to the TDO for examination. The EXTEST instruction also permits cluster testing, wherein components that do not incorporate boundary scan technology are tested. In cluster testing, data is shifted to the cluster/device input cells. Outputs from the cluster are captured by the input cells of a second boundary-scan device. The captured data is then shifted out of the second boundary-scan device for examination.
The BYPASS instruction allows the TDO buffer to generate the same bit stream as TDI. This is done by placing a single shift-register, called the bypass register, between TDI and TDO. When one does not wish to test a particular component, but the test data sequence must shift through that component to test another device, the BYPASS instruction is issued to that particular component to bypass the test data sequence.
The SAMPLE/PRELOAD instruction permits the execution of two functions: it allows sampling of normal operation data at the periphery of a component, and placing of an initial data pattern at latched parallel outputs of the boundary-scan cells. This instruction is used to load data onto the latched outputs prior to selection of another test instruction, such as the EXTEST instruction.
As with BIST, boundary scan technology requires an increase in the silicon area to accommodate the TAP system and the input and output boundary-scan registers.
The general acceptance of boundary scan by the designer and the Automatic Test Equipment (ATE) community makes boundary scan an effective test strategy. The incorporation of BIST with the boundary scan registers and the TAP controller provides a flexible framework at all levels of testing--chip level, board level and system level.
Although the use of BIST in a boundary scan environment has been proposed beforehand, the traditional approach is to provide separate hardware for performing BIST and boundary scan test. This increases the hardware overhead incurred.